As dimensions of semiconductor devices decrease, the available process window size decreases and manufacturing design rules shrink requiring tighter control over the manufacturing process. Generally, improvements in semiconductor fabrication (processes) or improvements in structural fabrication are required in order to further decrease critical dimensions and, thereby semiconductor devices. However, tighter control over the manufacturing process can be difficult to achieve, especially as critical dimension decrease further.
Semiconductor fabrication is a manufacturing process employed to create semiconductor devices in and on a wafer surface. Polished, blank wafers come into semiconductor fabrication, and exit with the surface covered with large numbers of semiconductor devices. Semiconductor fabrication includes a large number of steps and/or processes that control and build the devices—basic processes utilized are layering, patterning, doping and heat treatments. Layering is an operation that adds thin layers to the wafer surface. Layers can be, for example, insulators, semiconductors and/or conductors and are grown or deposited via a variety of processes. Some common deposition techniques are chemical vapor deposition (CVD), evaporation and sputtering. Patterning is a series of steps that results in the removal of selected portions of surface layers. After removal, a pattern of the layer is left on the wafer surface. The material removed can be, for example, in the form of a hole in the layer or a remaining island of the material. The patterning transfer process is also referred to as photomasking, masking, photolithography or microlithography. The actual subtractive patterning, i.e. removal of material from the surface film, is done by plasma etching. The goal of the patterning process is to create desired shapes in desired dimensions (e.g., feature size) as required by a circuit design and to locate them in their proper location on the wafer surface. Patterning is generally considered the most important of the four basic processes. Doping is the process that adds specific amounts of dopants to the wafer surface. The dopants can cause the properties of layers to be modified (e.g., change a semiconductor to a conductor). A number of techniques, such as thermal diffusion and ion implantation can be employed for doping. Heat treatments are another basic operation in which a wafer is heated and cooled to achieve specific results. Typically, in heat treatment operations, no additional material is added or removed from the wafer, although contaminates and vapors may evaporate from the wafer. One common heat treatment is annealing, which repairs damage to crystal structure of a wafer/device generally caused by doping operations. Other heat treatments, such as alloying and driving of solvents, are also employed in semiconductor fabrication.
A particularly important fabrication process employed in memory devices and logic devices is the polysilicon gate etch process that forms the polysilicon gate, which is typically utilized for a transistor. This etch process is important in terms of device operation and critical dimensions. Better or tighter control of the etch process results in benefits such as: a) better device characteristics; b) improved device performance; and/or c) improved device yield. Collectively these benefits improve device yield and/or produce devices with additional intrinsic value (e.g., better performance, lower heat dissipation, lowered leakage current). Thus, a stable, accurate and precise polysilicon gate etch process is vital for economic viability of devices in the marketplace.
There are a number of conventional methods and/or systems for controlling gate etch CD. One conventional system is an end point detection system. End point detection systems operate by monitoring selected process observables such as optical emission from plasma, de bias voltage, RF impedance, intensity of laser light reflected from the wafer, a refraction pattern of a broadband light source and the like. Detection of a change, which is associated with the end of the etch process, triggers an alarm causing the etch tool to halt the process with a suitable allocation of over etch time based on the process requirements and chemistry.
Another method involves control models that allow or assist control of the etch time. For this approach, the significant parameter of interest is the etch rate. Given the etch rate for a particular process, input measurements can be performed to determine the total film depth or thickness (measured perpendicular to the wafer surface) that needs to be etched. The etch time is then simply computed by dividing the total distance by the etch rate.
However, these conventional approaches typically utilize a simple linear control model. End point detection employs measurement of process observables to determine when to stop etching whereas the control model approach computes an expected etch time based on the etch rate and the etch distance as input parameters. These approaches are essentially controlled by the amount of etch time (e.g., directly utilizing etch distance and indirectly utilizing end point detection). Additionally, these approaches only consider etching in the vertical dimension, (i.e., perpendicular to the wafer surface) referred to as anisotropic but fail to consider etch rates in other directions such as horizontal or sideways etching, which is typically referred to as isotropic etching. Thus, the conventional approaches are limited in that they are unable to control horizontal etch rates and thereby, unable to adequately control horizontal dimensions of polysilicon gates. The conventional approaches do not enable further reductions in polysilicon gate critical dimensions because of this lack of control.